1. Field of the Invention
The present invention is related to static random access memories (SRAMs) and more particularly to improving noise sensitivity in SRAM cells.
2. Background Description
Invertors made completely of n-type enhancement mode field effect transistors (NFETs) or devices, such as inverter 20 of FIG. 1 are well known in the art. A typical NFET invertor 20 is two series connected NFETs 22, 24. The first NFET 22 is tied gate to drain between a supply voltage (Vdd) and an output 26. The second NFET 24 is connected drain to source between a low supply or reference voltage (ground, GND) and the output 26. The input 28 to the invertor 20 is provided to the gate of the second NFET 24.
With the input low, both FETs 22, 24 are off and the output is high, below Vdd by the NFET threshold voltage (VT), i.e., at Vddxe2x88x92VT. When the input to the invertor 20 is driven high, the second NFET 24 turns on and, at steady state is in its linear or resistive operating range (Ron), pulling the output 26 low. The first NFET is also on, but in saturation, acting as a voltage controlled current source (Isat) The output down level (Vlow) under these conditions is the voltage drop across the resistive second transistor 24 by the current supplied by the voltage controlled current source of the first transistor 22, i.e., Vlow=IsatRon. Calculating these parameters is well known in the art and is dependent upon device operating conditions and numerous technology dependent device characteristics.
Some of these device characteristics, e.g., gate oxide thickness, are common to both transistors 22, 24. However, the individual transistors 22, 24 each have individual device characteristics and bias conditions that affect Vlow, e.g., each device""s width to length ratio (W/L), gate, source and drain operating voltages and substrate bias voltage. A typically acceptable output down level is a voltage level that is somewhat less than VT such that the circuit driven by the invertor output 26 experiences a low, i.e., the next driven NFET does not turn on.
For simplicity in design, since at steady state the output is constant at Vlow very often each of the NFETs 20, 24 are modeled as resistors (transconductances) in a voltage divider. Accordingly, the output down level may be treated as the voltage from this voltage divider. Further, the ratio of these two transconductances may be referred to as the beta (xcex2) ratio of the invertor. The xcex2 ratio can be used to provide a measure of acceptability of the two devices 22, 24 as an invertor, i.e., a xe2x80x9crule of thumb.xe2x80x9d For example, an invertor with a xcex2 ratio of 1 has an output down level that is Vdd/2. An invertor with a xcex2 ratio of four has an output down level of 0.2Vdd.
FIG. 2 shows an example of a typical state of the art six transistor (6T) static random access memory (SRAM) cell 50, in the well-known complementary insulated gate FET technology known as CMOS. Data is stored in a pair of cross-coupled invertors 52, 54. NFET 52N and p-type FET (PFET) 52P form the first invertor 52. NFET 54N and PFET 54P form the second invertor 54. A pair of pass gates 56, 58 are connected between each of the cross coupled invertors 52, 54 and a respective bit line pair 60, 62. A word line 64, connected to numerous SRAM cells 50, controls the gates of pass gates 56, 58. Typically, the bit line pair 60, 62 are connected to numerous identical SRAM cells 50, each connected to a different word line. The capacitive load for the bit line cells is modeled by a pair of capacitors 66, 68. Each cell 50 is addressed/selected by intersection of the word line 64 at a bit line pair 60, 62.
In a typical SRAM array, a single word line 64 drives pass gates 56, 58 for numerous cells 50, each connected to individual pairs of bit lines 60, 62. Typically, anytime the word line is driven, only a subset of all of the cells at specific selected columns on the word line are of interest. Other cells on the word line at columns other than selected columns are also connected to their bit lines, typically referred to as half selected cells. The half selected cells are connected to their pre-charged bit line pairs with the bit line pairs precharged and floating at Vdd. Half selected cells should retain data after selection, identically to what is stored in them prior to half selection. A cell disturb, e.g., from incomplete precharge or a design imbalance, cells may switch states.
Data is written into the cell 50 by driving one of the bit line of the pair, 60, 62 high, pulling the other low and, subsequently, driving the word line 64 high for a short period of time. With the word line 64 high, the state of the bit line pair 60, 62 is transferred to cross coupled invertors 52, 54. With the word line 64 low, that state is stored in the cell 50.
Reading data stored in the cell is, more or less, the reverse of a write. First, the bit lines are pre-charged to some bit line pre-charge voltage level (Vpre), typically Vdd. After the bit lines are pre-charged, pre-charging the bit line capacitance is 66, 68, the bit lines are floated at the pre-charged and then the word line 64 is driven high. Whatever is stored in the cell, as represented by the respective complementary states of a cross coupled invertors 52, 54, is transferred to the bit lines 60, 62 as a voltage difference. Depending on the state of the cross couple invertors 52, 54, a corresponding bit line 60 or 62, eventually is pulled low and the remaining bit line 62 or 60 remains high. How fast the bit line is pulled low determines cell read time or read performance.
During a read, when the word line 64 turns on, both pass gates 56, 58 connect the cell storage nodes at the cross couple invertors 52, 54 to the bit line pair 60, 62. At least at the beginning of the read with both bit lines of the pair 60, 62 and the word line high, one of the cross coupled invertors 52, 54 (i.e., the invertor driving a low) is biased identically to the NFET inverter 20 of FIG. 1. Thus, cell stability depends on the xcex2 ratio of the particular pass gate/inverter NFETs 56/52N and 58/54N. Cell performance also depends on the xcex2 ratio for the pair of NFETs 56, 52N or 58, 54N pulling down the particular bit line 60 or 62 respectively.
Primary concerns of SRAM cell design are cell size, cell performance and cell stability. Cell size is usually a function of the particular geometry or minimum feature size available for the technology in which the cell is being made. Performance and stability are also affected by cell size. To minimize read time and, therefore, optimize performance, the resistance of both pass gates and inverter NFETs (52N, 54N, 56, 58) should be minimized. Typically, invertor NFETs 52N, 54N are a minimum sized devices. So, most read performance is realized by reducing the resistance of pass gates 56, 58. However, reducing the pass gate resistance increases transconductance, reducing xcex2 ratio and stability, e.g., by increasing the half select voltage drop across the internal cell NFETs 52N, 54N. Further, at some point xcex2 ratio may be low enough that even minor noise may cause the half selected cell to switch, inadvertently changing data stored in the cell. Generally, the cell beta ratio is selected between two and four, making SRAM cells are more stable and tolerant to noise and other disturbances, e.g., during a cell read. Also, in this xcex2 ratio range, the cell remains relatively insensitive to other sources of errors, e.g., alpha-particles or soft errors. Unfortunately, a more stable cell is harder to switch, thus increasing cell write time and also, this stability is at a cost of cell read performance which is not a particularly desirable tradeoff.
Cells with a beta ratio below 1.5 are considered sensitive with disturb occurring in as many as half of cells on a word line. At worst, the disturbs cause half selected cells to change states inadvertently, e.g., from 0 to 1 and vice versa. In particular minor cell mismatches in these sensitive cells, e.g., from poor process control or introduced in cell layout, that might otherwise be tolerable become intolerable at low voltages. So, cell designers are faced with opting for cell stability by keeping the cell xcex2 ratios between two and four and suffering long read and write times or, for performance by reducing the cell xcex2 ratios to below two and accepting/suffering the resulting cell sensitivity and instability.
It is a purpose of the invention to reduce the sensitivity of SRAM cells storing critical data;
It is a further purpose of the invention to improve SRAM cell performance;
It is yet another purpose of the invention to facilitate SRAM operation at low voltages.
The present invention is a static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. A first portion, cells have a low xcex2 ratio for high performance. A second portion of the array contains SRAM cells with a higher xcex2 ratio that are more stable than the cells in the first portion, but are somewhat slower.